Our group is investigating various accelerator architectures for compute-intensive machine learning applications, where we employ an algorithm-hardware co-design approach to achieving both high performance and low energy.

we are developing HeteroCL, a highly productive multi-paradigm programming infrastructure that explicitly embraces heterogeneity to integrate a variety of programming models into a single, unified programming interface.

We are developing a new generation of HLS techniques that feature scalable cross-layer synthesis and exact optimization, complexity-effective dynamic scheduling, trace-based analysis, and information flow enforcement to enable a greatly simplified hardware design experience, while achieving a high performance and satisfying the ...

We believe there is a great potential for employing ML across different stages of the design automation stack to expedite design closure by (1) minimizing human supervision in the overall design tuning process and (2) significantly reducing the time required to obtain accurate QoR estimation for a given design point....