Zhang Research Group

Accelerating Design of Future Computing Systems

Computer Systems Lab, Cornell University

FCCM'22, Cornell Tech
Computer Systems Lab
Zhang Zooms
Bowling Social!
HeteroCL

Recent News

[03/01/22] SDC scheduling inducted into ACM/SIGDA TCFPGA Hall of Fame! [Paper Link]

[03/01/22] RapidStream Received the FPGA'22 Best Paper Award! [Paper Link]

[01/19/22] Xiuyu Receives the Honorable Mention of 2022 CRA Outstanding Undergraduate Researcher Award!

[01/16/22] HeteroFlow and HiSparse Accepted to FPGA 2022!

[12/18/21] Congrats Sean, Yuan, and Amazon AWS!

[11/15/21] Pangenomics through the Panorama Project!

[10/28/21] GraphLily Accepted to ICCAD 2021!

[09/16/21] Welcome to New Students in 2021!

[09/06/21] Prof. Zhiru Zhang gives a plenary talk in MLCAD 2021

More News

Research Projects

Algorithm-Hardware Co-Design for Machine Learning Acceleration

Our group is investigating various accelerator architectures for compute-intensive machine learning applications, where we employ an algorithm-hardware co-design approach to achieving both high performance and low energy.

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Multi-Paradigm Programming for Heterogeneous Platforms

we are developing HeteroCL, a highly productive multi-paradigm programming infrastructure that explicitly embraces heterogeneity to integrate a variety of programming models into a single, unified programming interface.

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High-Level Synthesis of Fast and Secure Accelerators

We are developing a new generation of HLS techniques that feature scalable cross-layer synthesis and exact optimization, complexity-effective dynamic scheduling, trace-based analysis, and information flow enforcement to enable a greatly simplified hardware design experience, while achieving a high performance ...

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Learning-Assisted IC Design Closure

We believe there is a great potential for employing ML across different stages of the design automation stack to expedite design closure by (1) minimizing human supervision in the overall design tuning process and (2) significantly reducing the time required to obtain accurate QoR estimation for a given design point ...

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