Zhang Research Group

Accelerating Design of Future Computing Systems

Computer Systems Lab, Cornell University

Computer Systems Lab
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We are developing HeteroCL, a highly productive multi-paradigm programming infrastructure.
Heterogeneous Computer Architectures

Recent News

[04/05/2021] Edge Survey Published in IEEE D&T [Paper Link]

[03/29/2021] Logic Distillation Paper Accepted to DAC'21!

[03/15/2021] Dagger Accepted to ASPLOS'21! [Paper Link]

[03/04/2021] AutoBridge Received the FPGA'21 Best Paper Award! [Paper Link]

[02/15/2021] Welcome to Yaohui Cai!

[01/13/2021] FracBNN Selected as FPGA'21 Best Paper Candidates [Paper Link]

[11/24/2020] GLAIVE Accepted to DATE'21 [Paper Link]

[11/19/2020] Prof. Zhiru Zhang gives a talk in ECE Colloquium Series

[10/27/2020] Prof. Zhiru Zhang gives a talk at the Samsung Forum

[10/15/2020] Ecenur Selected for Rising Stars in EECS 2020

[09/20/2020] TECHCON 2020 Presentations and Awards

[08/02/2020] IWLS2020 Keynote and Contest Winner

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Research Projects

Algorithm-Hardware Co-Design for Machine Learning Acceleration

Our group is investigating various accelerator architectures for compute-intensive machine learning applications, where we employ an algorithm-hardware co-design approach to achieving both high performance and low energy.

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Multi-Paradigm Programming for Heterogeneous Platforms

we are developing HeteroCL, a highly productive multi-paradigm programming infrastructure that explicitly embraces heterogeneity to integrate a variety of programming models into a single, unified programming interface.

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High-Level Synthesis of Fast and Secure Accelerators

We are developing a new generation of HLS techniques that feature scalable cross-layer synthesis and exact optimization, complexity-effective dynamic scheduling, trace-based analysis, and information flow enforcement to enable a greatly simplified hardware design experience, while achieving a high performance ...

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Learning-Assisted IC Design Closure

We believe there is a great potential for employing ML across different stages of the design automation stack to expedite design closure by (1) minimizing human supervision in the overall design tuning process and (2) significantly reducing the time required to obtain accurate QoR estimation for a given design point ...

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