Zhang Research Group

Accelerating Design of Future Computing Systems

Computer Systems Laboratory

Cornell University

Computer Systems Lab
Bowling Social!
Group Picture
We are developing HeteroCL, a highly productive multi-paradigm programming infrastructure.
Heterogeneous Computer Architectures

Recent News

[10/15/2020] Ecenur Selected for Rising Stars in EECS 2020

[09/20/2020] TECHCON 2020 Presentations and Awards

[08/02/2020] IWLS2020 Keynote and Contest Winner

[07/17/2020] Two Papers Accepted to ICCAD 2020

[07/09/2020] Facebook Research Award for Graph Learning

[07/08/2020] MatRaptor accepted to MICRO 2020

[01/15/2020] Farewell Nitish!

[12/19/2019] Two papers accepted to ICLR 2020 from our group.

[12/13/2019] Prof. Zhang gave invited talks at the TVM conference and NeurIPS'19.

[11/19/2019] Prof. Zhang received the Ruth and Joel Spira Award for Excellence in Teaching.

More news

Research Projects

Algorithm-Hardware Co-Design for Machine Learning Acceleration

Our group is investigating various accelerator architectures for compute-intensive machine learning applications, where we employ an algorithm-hardware co-design approach to achieving both high performance and low energy.

Learn more...

Multi-Paradigm Programming for Heterogeneous Platforms

we are developing HeteroCL, a highly productive multi-paradigm programming infrastructure that explicitly embraces heterogeneity to integrate a variety of programming models into a single, unified programming interface.

Learn more...

High-Level Synthesis of Fast and Secure Accelerators

We are developing a new generation of HLS techniques that feature scalable cross-layer synthesis and exact optimization, complexity-effective dynamic scheduling, trace-based analysis, and information flow enforcement to enable a greatly simplified hardware design experience, while achieving a high performance ...

Learn more...

Learning-Assisted IC Design Closure

We believe there is a great potential for employing ML across different stages of the design automation stack to expedite design closure by (1) minimizing human supervision in the overall design tuning process and (2) significantly reducing the time required to obtain accurate QoR estimation for a given design point ...

Learn more...