[02/28/23] HeteroCL v0.5 released!

[01/10/23] Zhang Research Group Joined the ACE Center for Evolvable Computing

[12/06/22] Prof. Zhiru Zhang elevated to IEEE Fellow

[11/24/22] GARNET is accepted to LoG'22 as a spotlight paper.

[10/13/22] Ecenur Üstün successfully defends her dissertation. Good luck, Ecenur!

[09/15/22] Chenhui and Andrew win the 2022 Qualcomm Innovation Fellowship!

[05/26/22] Prof. Zhang Chaired the IEEE FCCM 2022 Conference at Cornell Tech, NYC

[03/01/22] SDC scheduling inducted into ACM/SIGDA TCFPGA Hall of Fame! [Paper Link]

[03/01/22] RapidStream Received the FPGA'22 Best Paper Award! [Paper Link]

[01/19/22] Xiuyu Receives the Honorable Mention of 2022 CRA Outstanding Undergraduate Researcher Award!

[01/16/22] HeteroFlow and HiSparse Accepted to FPGA 2022!

[12/18/21] Congrats Sean, Yuan, and Amazon AWS!

[11/15/21] Pangenomics through the Panorama Project!

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Algorithm-Hardware Co-Design for Machine Learning Acceleration

Our group is investigating various accelerator architectures for compute-intensive machine learning applications, where we employ an algorithm-hardware co-design approach to achieving both high performance and low energy.

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Multi-Paradigm Programming for Heterogeneous Platforms

we are developing HeteroCL, a highly productive multi-paradigm programming infrastructure that explicitly embraces heterogeneity to integrate a variety of programming models into a single, unified programming interface.

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High-Level Synthesis of Fast and Secure Accelerators

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Learning-Assisted IC Design Closure

We believe there is a great potential for employing ML across different stages of the design automation stack to expedite design closure by (1) minimizing human supervision in the overall design tuning process and (2) significantly reducing the time required to obtain accurate QoR estimation for a given design point ...

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