ARIES Paper Accepted to FPGA 2025 and Nominated for Best Paper!

In collaboration with Brown University, ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines, has been accepted to the International Symposium on Field-Programmable Gate Arrays 2025 and nominated for the Best Paper Award!

ARIES tackles the growing complexity of programming AMD’s AI Engine (AIE) architectures by introducing a flexible and unified MLIR-based compilation flow. It dramatically boosts programming productivity by enabling seamless mapping of tasks across AIE cores and FPGA fabric, all while supporting fine-grained instruction-level and tile-level parallelism through a clean abstraction. With impressive throughput on GEMM and up to 22.58× speedup on ResNet layers compared to state-of-the-art, ARIES sets a new standard for performance and portability in reconfigurable computing.

Congratulations to the authors!

Check it out on GitHub: https://github.com/arc-research-lab/Aries.

Read the paper here.


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