John Jiang

PostDoc (Starting S’16)

Computer Systems Laboratory
School of Electrical and Computer Engineering
Cornell University

Office: 471F Rhodes Hall, Ithaca, NY 14853
Email: jz763 -at- (personal website)

About Me

I am a Postdoctoral Research Associate under the supervision of Prof. Zhiru Zhang in the Computer Systems Laboratory (CSL) at Cornell University. My research interests are High-Level Synthesis and Hardware Security.

I received my Ph.D. degree in Microelectronics and Solid State Electronics from Institute of Electronics, Chinese Academy of Sciences (Beijing, China) in 2016. I have a B.S. in Electronic Science and Technology from Huazhong University of Science and Technology.


  • Jiang, Zhenghong, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, and Paolo Ienne. “A technology mapper for depth-constrained FPGA logic cells.” In Field Programmable Logic and Applications (FPL), 2015 25th International Conference on, pp. 1-8. IEEE, 2015.
  • Jiang, Zhenghong, Colin Yu Lin, Liqun Yang, Fei Wang, and Haigang Yang. “Exploring architecture parameters for dual-output LUT based FPGAs.” In Field Programmable Logic and Applications (FPL), 2014 24th International Conference on, pp. 1-6. IEEE, 2014.
  • Lin, Colin Yu, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So, and Haigang Yang. “FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels.” ACM SIGARCH Computer Architecture News 44, no. 4 (2017): 92-97.
  • Huang, Zhihong, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, and Haigang Yang. “NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element.” In Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 135-140. ACM, 2017.


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