Our research group investigates cross-cutting research topics at the intersection of design automation, compiler optimization, and computer architecture at multiple scales, from circuit-level building blocks, to chip-level processor & coprocessor cores, to system-level heterogeneous compute nodes that integrate CPUs, GPUs, and reconfigurable logics. We take a software/hardware co-design approach to addressing challenging research problems that require rethinking of the design methodologies, CAD optimizations, and compute substrates to enable significantly accelerated implementation and application of future computing systems.

Comments are closed